1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device and a semiconductor system including the same for performing a mirror function.
2. Description of the Related Art
Recently, a semiconductor system uses a package structure of a mirror type to implement a high integration, a high band width and a high capacity thereof. For example, a first semiconductor device is mounted on a side of a substrate, and a second semiconductor device is mounted on the other side of the substrate so that the first semiconductor device is opposite to the second semiconductor device.
If the first semiconductor device and the second semiconductor device are fabricated in a same chip, a pad array of the first semiconductor device is symmetric to a pad array of the second semiconductor device. The first semiconductor device and the second semiconductor device may obtain a same signal through pads, which are opposite to each other based on a mirror function. That although the pads are included in the first semiconductor device and the second semiconductor device, respectively, the same signal inputted through the pads may be re-applied in the first semiconductor device and the second semiconductor device.
For example, if the a predetermined signal is applied to a first pad of the first semiconductor device, which is opposite to a second pad of the second semiconductor device, the predetermined signal is not re-distributed to the first semiconductor device through the first pad due to an inactivation of a mirror function while the predetermined signal is re-distributed to the second semiconductor device through the second pad due to an activation of a mirror function. Meanwhile a differential signal such as a clock signal is transferred through a direct routing path without being re-distributed.
FIG. 1 is a block diagram illustrating a conventional semiconductor system. FIG. 2 shows a routing path on a substrate between a first semiconductor device and a second semiconductor device shown in FIG. 1.
Referring to FIG. 1, the semiconductor system includes a controller 10, a first semiconductor device 20, a second semiconductor device 30, and a substrate 40.
The controller 10 generates differential clock signals CLK and CLKB and a reset signal RESETB. The controller 10 includes a processor such as a graphic processing unit (GPU), and controls an operation of the first semiconductor device 20 and the second semiconductor device 30.
The first and second semiconductor devices 20 and 30 perform a predetermined function in response to the differential clock signals CLK and CLKB and the reset signal RESETB, respectively. The first and second semiconductor devices 20 and 30 may include a dynamic random access memory (DRAM), and may be mounted on a substrate 40 in a symmetric structure corresponding to a mirror function. The first and second semiconductor devices 20 and 30 may include first pads (not shown which receive the differential clock signals CLK and CLKB and the reset signal RESETB. The first and second semiconductor devices 20 and 30 may include second pads (not shown), which receive a mirror function activation signal MF for controlling an activation of a mirror function. The mirror function activation signal MF indicates whether the first semiconductor device 20 and the second semiconductor device 30 perform the mirror function or not.
For example, if the second semiconductor device 30 is set to a mirrored semiconductor device, the first semiconductor device 20 does not activate a mirror function based on the second pad for the mirror function activation signal MF, which is coupled to a ground voltage (VSS) terminal, and the second semiconductor device 30 activates a mirror function based on the second pad for the mirror function activation signal MF, which is coupled to a power supply voltage (VDD) terminal.
The substrate 40 between the controller 10 and the first and second semiconductor devices 20 and 30 routes the differential clock signals CLK and CLKB and the reset signal RESETB. That is, the substrate 40 provides a routing path for transferring the differential signal's CLK and CLKB, the reset signal RESETB and the mirror function activation signal MF.
Especially, referring to FIG. 2, the substrate 40 provides a routing path for directly transferring the differential clock signals CLK and CLKB to pads PD1 and PD2 in the first pads of the first semiconductor device 20 and the second semiconductor device 30. In FIG. 2, the pad PD1 for receiving a positive clock signal CLK of the first semiconductor device 20 is opposite to the pad PD2 for a negative clock signal CLKB of the second semiconductor device 30, and the pad PD2 for the negative clock signal CLKB of the first semiconductor device 20 is opposite to the pad PD1 for the positive clock signal CLK of the second semiconductor device 30, on the basis of the substrate 40L
However, in the conventional semiconductor system, a plurality of pads, which receive various signals provided from the controller 10, are physically coupled to the first and second semiconductor devices 20 and 30. Especially, the pads PD1 and PD2 directly receive the differential dock signals CLK and CLKB through the substrate 40 without supporting a mirror function. Thus, design for the routing path for transferring the differential dock signals CLK and CLKB may become complex and occupy a wide area.
Moreover, since the second pads for the mirror function activation signal MF are independently disposed in the first and second semiconductor devices 20 and 30, an area for the second pads for the mirror function activation signal MF may be occupied in the first and second semiconductor devices 20 and 30.